The present invention relates to computer architecture and, more specifically, to scheduling and prioritizing store and fetch requests to computer memory.
For some computing system processors, an associated cache cannot execute a fetch and store request in the same cycle. As processor speeds increase, detection of a conflict of a fetch and store request becomes increasingly more difficult, as the system must know of a conflict well in advance in order to stall or delay execution of one of the requests. In one approach, a process attempts to predict the occurrence of a conflict many cycles before the attempted execution of the request. To accommodate high-frequency designs, the process for predicting conflicts can over-indicate conflicts. This inaccuracy, causes unnecessary delays of fetch and/or store requests. These postponed requests can lead to undesirable performance penalties for the computing system.